1. Field of the Invention
The present invention relates to an interface apparatus, which is adapted as an interface between calculation units that perform data transmission by using address allocation, a calculation processing apparatus, an interface generation apparatus, and circuit generation apparatus.
2. Description of the Related Art
In general, in order to perform data transmission by address allocation, a large-capacity storage device is disposed between calculation units (for example, refer to Japanese Patent No. 3644380).
FIG. 1 is a block diagram illustrating an example of a calculation processing apparatus employing a general data transmission method.
The calculation processing apparatus 10 shown in FIG. 1 includes a first calculation unit 11, a second calculation unit 12, a main storage unit 13, and an address selector 14.
In addition, in FIG. 1, WDT, WADR, WCTL, RDT, RADR, and ADR denotes write data, a write address, a write control signal, read data, a read address, and a selected address, respectively.
In the calculation processing apparatus 10 shown in FIG. 1, the write data WDT output from the first calculation unit 11 are stored at a position allocated with the write address WADR in the main storage unit 13.
Next, in the calculation processing apparatus 10, the second calculation unit 12 reads data at a position allocated with the read address RADR from the storage device, so that the data transmission from the first calculation unit 11 to the second calculation unit 12 is performed.
In addition, in general, in the case where the transmission rate of the large-capacity main storage unit is low and too much time is taken for the data transmission, a cache memory is disposed between the calculation unit and the main storage unit (for example, refer to Japanese Unexamined Patent Application Publication No. 8-16467).
FIG. 2 is a block diagram illustrating an example of a calculation processing apparatus using a cache memory.
A calculation processing apparatus 10A shown in FIG. 2 is configured by disposing a cache memory 15 to the configuration of the calculation processing apparatus 10 shown in FIG. 1.
In the calculation processing apparatus 10A of FIG. 2, the write data WDT output from the first calculation unit 11 are temporarily written in the small-capacity, high-rate cache memory 15. Next, the second calculation unit 12 reads the data allocated with the read address RADR from the cache memory 15, so that the data transmission from the first calculation unit 11 to the second calculation unit 12 is performed.
The cache memory 15 periodically writes the write data WDT stored in the cache memory 15 in the main storage unit 13 in a collective manner.
In addition, in the case where the data allocated with the read address RADR do not exist in the cache memory 15, the cache memory 15 reads data from a storage device corresponding to the read address RADR in the main storage unit 13 and outputs the data as the read data RDT.
In the data transmission method shown in FIG. 1, since it is necessary that the main storage unit has the storage devices uniquely corresponding to the addresses indicated by the write address WADR and the read address RADR, large-capacity storage devices have to be provided, so that there is a disadvantage in that the area of circuits is increased.
For example, in the technology disclosed in Japanese Patent No. 3644380, as shown in FIG. 13 of Japanese Patent No. 3644380, when two processors communicate with each other, it is necessary that a main memory connected to a memory controller is used. Therefore, there is a disadvantage in that the large-capacity storage devices have to be provided.
In the data transmission method shown in FIG. 2, the number of times of accessing a low-rate main storage unit 13 is reduced, so that high-rate data transmission may be effectively implemented.
However, since it is necessary that the main storage unit 13 has storage devices uniquely corresponding to the addresses ADR indicated by the write address WADR and the read address RADR, large-capacity storage devices have to be provided, so that the disadvantageous problem in that the area of circuits is increased is not solved.
For example, in the technology disclosed in Japanese Unexamined Patent Application Publication No. 8-16467, as shown in FIG. 1 of Japanese Unexamined Patent Application Publication No. 8-16467, in the related art, the cache memory temporarily stores the data read from the main memory or temporarily stores the data that are to be written in the main memory.
Therefore, in the configuration of the technology, the data transmission may not be performed without the main memory. Since it is necessary that the storage devices uniquely corresponding to the addresses are provided, there is a disadvantage in that the large-capacity storage devices must be provided to the main memory.
As described above, in the configuration shown in FIGS. 1 and 2, if there is no large-capacity storage device uniquely corresponding to the addresses output from the calculation unit, there is a problem in that the data transmission may not be performed.
Therefore, there is contrived a configuration where the main storage unit is removed from the configuration of FIG. 2, and as shown in FIG. 3, the first calculation unit 11 and the second calculation unit 12 communicate with each other by using only the cache memory 15.
According to the configuration, a capacity of a storage device that is necessary for the interface apparatus may be reduced.
However, in the configuration shown in FIG. 3, although there are data that are not read by the second calculation unit 12, the first calculation unit 11 updates the contents of the cache memory 15, and thus, there is a problem in that the data necessary for the second calculation unit 12 may be overwritten. In this case, the data transmission may not be properly performed.
In addition, in the configuration shown in FIG. 3, there is a problem in that it is necessary to increase the number of data stored in the cache memory 15 so as to reduce concerns that the data transmission will be incorrectly performed.